thanks Nvidia, maybe 4gb VRAM is next
Noone will ever need more than 640k of RAM
- no one
Achshully, you’re right
Isn’t vram usually bigger than ram? Those pics should be switched.
EDIT: Oh, I took vram to be virtual ram, not video ram. It makes sense for video ram.
Mine certainly isn’t. 6GB vram, 16gb ram.
It depends on your definition of “usually”, high end GPUs for data centers, AI, workstations or “enthusiasts” yea. For these applications you’re starting at like 16
GPUs for us plebs, no
It’s also fairly cheap to buy 32+ GB of RAM, lots of choices for under $80. Meanwhile, I’m not even sure how you find a video card with 32GB of VRAM (not that you really need this much, 12GB and 16GB are pretty solid for a video card nowadays).
Creating your swap as 2x your RAM is outdated advice. Now it’s essentially changed to be 2x until 4GB of RAM, then 1x until 8GB, and anything over 8GB just use 4GB of swap because you probably have enough RAM. Or, even some modern systems like Fedora will swap to zRAM. Which is just a highly compressed portion of RAM.
RAM on phones is ok, though.
Generally there’s a reverse relationship between size and speed. A 8gb cache would also be super slow thus defeating the purpose of the cache. If it were so easy every cpu would have a huge cache
What does 1GB of cache look like?
The meme don’t make sense. An SRAM cache of that size would be so slow that you would most likely save clock cycles reading directly from RAM an not having a cache at all…
Slow? Not necessarily.
The main issue with that much memory is the data routing and the physical locality of the memory. Assuming you (somehow) could shrink down the distance from the cache to the registers and could have a wide enough data line/request lines you can have data from such a cache in ~4 cycles (assuming L1 and a hit).
What slows down memory for L2 is the wider address space and slower residence checks. L3 gets a bit slower because of even wider address spaces but also it has to deal with concurrency issues since it’s shared among cores. It also ends up being slower because it physically has to be further away from the cores due to it’s size.
If you ever look at a CPU die, you’ll see that L1 caches are generally tiny and embedded right into the center of the processor. L2 tends to be bolted onto the sides of the physical cores. And L3 tends to be the largest amount of silicon real estate on a CPU package. This is all what contributes to the increasing fetch performance for each layer along with the fact that you have to check the closest layers first (An L3 hit, for example, means that the CPU checked L1 and L2 and failed at both which takes time. So L3 access will always be at least the L1 + L2 times).
I agree. When evaluating cache access latency, it is important to consider the entire read path rather than just the intrinsic access time of a single SRAM cell. Much of the latency arises from all the supporting operations required for a functioning cache, such as tag lookups, address decoding, and bitline traversal. As you pointed out, implementing an 8 GB SRAM cache on-die using current manufacturing technology would be extremely impractical. The physical size would lead to substantial wire delays and increased complexity in the indexing and associativity circuits. As a result, the access latency of such a large on-chip cache could actually exceed that of off-chip DRAM, which would defeat the main purpose of having on-die caches in the first place.
that much cache could be detrimental to the speed of your CPU
Still remember my first 500MB drive, thought I would never manage to fill it up
8GB of (internet) bandwidth.
The first computer I bought had eight megs of RAM.
I remember being thrilled with a 20 meg scsi hard drive I got as a kid.
I have an 8gb ATA storage drive on my desk… wonder if it stills works
